1. Field of the Invention
The present invention relates to a bidirectional input and output (I/O) interface circuit used for inputting and outputting data to and from an integrated circuit and, particularly, to an I/O interface circuit of an integrated circuit in which a terminator in input mode and a driver in output mode are improved.
2. Description of Related Art
In a high-speed logic circuit where a signal rises and falls quickly, it is necessary to treat a signal line as a transmission line of a distributed constant circuit, in which signal reflection matters. The signal reflection occurs at a connection point between a transmission line and a circuit with different impedance from the characteristic impedance of the transmission line. If the characteristic impedance of the transmission line is Z0, the load impedance of the same is ZL, a reflection coefficient ρ1 at a receiving end is expressed as: ρ1=(ZL−Z0)/(ZL+Z0). If the output impedance of a signal source is ZS, a reflection coefficient ρ2 at a transmitting end is expressed as: ρ2=(ZS−Z0)/(ZS+Z0). Thus, the signal reflection is doesn't occur when the transmission line is terminated with ZL=Z0 or ZS=Z0. Hence, an I/O portion of an integrated circuit has a terminator for matching impedance of another circuit with the impedance of the transmission circuit.
I/O circuits of integrated circuits thus generally include an output circuit (output buffer), an input circuit (input buffer), and a termination circuit. However, since the output circuit and the termination circuit occupy a relatively large area, separate placement of the two circuits causes increase in a chip area.
Japanese Unexamined Patent Application Publication No. 2003-133943, for example, proposes an I/O circuit of a large-scale integrated circuit (LSI) which uses a part of an output circuit also as a termination circuit to reduce the occupation area. FIG. 11 is a circuit diagram which shows this I/O interface circuit in a way to clarify the relation to the present invention.
The I/O interface circuit 110 of FIG. 11 is connected to an I/O terminal 100 connected to a transmission line outside of the LSI. The I/O interface circuit 110 includes a driver 1 as an output circuit (output buffer) and an input circuit (input buffer) 5. In the driver 1, a plurality of pairs of P-channel (Pch) transistors 2 and N-channel (Nch) transistors 3 are connected in series between a supply voltage VDD and a ground voltage GND. The connection points between the Pch transistors 2 and Nch transistors 3 are all connected to the I/O terminal 100. A controller 4 supplies a control signal to each of the gates of the Pch transistors 2 and Nch transistors 3, thereby turning on or off the transistor.
In the case of using the I/O interface circuit 110 in input mode, an input enable signal IEN inputted to the input circuit 5 is set High, and an output enable signal OEN inputted to the controller 4 is set Low. During the input mode, data is inputted to the I/O terminal 100 (Y0), transmitted through the input circuit 5, and then supplied inside the LSI as a signal Y1. Meanwhile, since the output enable signal OEN is Low, the controller 4 outputs a signal to turn on both of the Pch transistor 2 and the Nch transistor 3 of the driver 1, thus forming a terminator (Thevenin terminator) R1.
On the other hand, in the case of using the I/O interface circuit 110 in output mode, the input enable signal IEN is set Low, and the output enable signal OEN is set High. During the output mode, a signal A is inputted to the controller 4, transmitted through the driver 1, and outputted from the I/O terminal 100. When the output enable signal OEN is High and the output signal A is High, the controller 4 outputs a signal to turn on the Pch transistor 2 and turn off the Nch transistor 3 of the driver 1. This turns on all the Pch transistors 2 in the driver 1, thereby outputting the supply voltage VDD through the I/O terminal 100. When the output enable signal OEN is High and the output signal A is Low, the controller 4 outputs a signal to turn off the Pch transistors 2 and turn on the Nch transistor 3 of the driver 1. This turns on all the Nch transistors 3 in the driver 1, thereby outputting the ground voltage GND through the I/O terminal 100. In this way, a signal of High (VDD) or Low (GND) is outputted through the I/O terminal 100 in accordance with High or Low of the output signal A.
As described above, the transistors of the driver 1 serve as the terminator (Thevenin terminator) in the input mode and as the driver transistor in the output mode. The output circuit is thus used also as the termination circuit, which reduces the chip occupation area.
It has now been discovered that the I/O interface circuit 110 cannot maintain constant termination resistance since the termination resistance varies depending on variation in process conditions and temperature changes.
Further, the I/O interface circuit 110 cannot maintain constant output impedance neither since the output impedance also varies depending on variation in process conditions and temperature changes.
It has now been also discovered that the I/O interface circuit 110 cannot match the impedance with the impedance of the transmission line in at least either input or output mode since load impedance in the input mode and output impedance in the output mode are different.